Patterning film stacks for three-dimensional (3D) memory devices can be difficult. Some conventional atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD) and plasma-enhanced chemical vapor deposition (PECVD) processes for depositing film layers may produce unacceptably rough films, cause unacceptable interfacial mixing between film layers, and may lead to interfacial defects caused by vacuum breaks between successively deposited film layers. The resulting rough film interfaces and interfacial defects may be magnified by subsequently deposited layers as the film stack is built, so that the top surface of the film stack may be unacceptably rough for downstream patterning processes. Further, interfacial defects within the film stack may lead to structural and/or electrical defects in the 3D memory device. In addition to roughness, stress values of deposited films present an important consideration.